1. Field of the Invention
The present invention relates to liquid crystal technology field, more particularly to a low temperature poly-silicon TFT based on dual-gate structure, an array substrate, and a method for manufacturing the TFT.
2. Description of the Prior Art
Low temperature poly-silicon (LTPS) is characterized by high carrier mobility. This characteristic is the backbone of development of LTPS thin film transistors (TFT). Designing associated integrated circuits (ICs) around a panel has been focused, and intensive research has been given to system on panel (SOP) technology. However, the characteristic of high carrier mobility of LTPS has made LTPS prone to current leakage in contrast to A-Si. Current leakage has become a critical issue of LTPS design.
Please refer to FIG. 1, showing a schematic diagram of a conventional LTPS N-TFT. The LTPS N-TFT includes a base 10, a buffer layer 11, a patterned ploy-silicon layer 12, an isolating layer 13, a gate layer 14, an insulating layer 15, and a source-drain layer 16. The patterned ploy-silicon layer 12 comprises a heavily doped source region 121 on one side, a heavily doped drain region 122 on the other side, and a channel 120 therebetween.
Electric current characteristics of a conventional LTPS TFT is highly influenced by the processes of forming ploy-silicon. The junction characteristic of ploy-silicon affects directly current leakage, threshold swing, and threshold voltage of LTPS TFT. In contrast to A-Si, the electric current and conductivity of the LTPS TFT are better due to higher mobility. However, the higher mobility causes more current leakage, thereby damaging operation of the component.
Refer to FIG. 2 showing a structure diagram of a conventional Lightly Doped Drain (LDD) Single-Gate N-type thin film transistor (N-TFT). The LDD Single-Gate N-TFT comprises two LDDs 223 between a heavily doped source 221 and a channel 220, and between a heavily doped drain 222 and the channel 220, respectively. The two LDDs 223 widen potential barriers between the source and channel 220 and between the drain and the channel 220.
The LDD 223 forms an intensity buffer causing a high resistance across the source-drain, so as to reduce a gradient of the electric field on the edge of the drain, reducing leakage current and avoiding hot carrier effect. Accordingly, the TFT as shown in FIG. 2 can leakage current of the component. Nevertheless, the TFT shown in FIG. 2 can not effectively reduce leakage current resulting from higher mobility. Specifically, leakage current is not neglectable in case that the characteristic of the component has been worse due to a long time use.
Refer to FIG. 3 showing a structure diagram of a conventional Lightly Doped Drain (LDD) Dual-Gate N-type thin film transistor. The Dual-Gate N-TFT comprises a gate layer 34 with a first gate area 341 and a second gate area 342.
The Dual-Gate N-TFT increases a length of the channel between the source and drain, effectively reducing the leakage current of the component. Such Dual-Gate N-TFT which has driving ability as the component shown in FIG. 2 is widely used in LCD devices, but its driving ability is poorer than the component shown in FIG. 1 due to the existence of the LDDs.